1. Field of the Invention
The present invention relates to a data processing system and method thereof, especially to utilize the inverse discrete cosine transform (IDCT) procedure to perform the system and method thereof of the IDCT procedure.
2. Description of the Prior Art
The digital video codec of the prior art utilizes a discrete cosine transform (DCT) procedure to compress digital data. For example, the international image code/decode standard (MPEG1, MPEG2, MPEG4, etc.) first divides each picture into N×N blocks, and N is equal to 8 in general. Then, in the image recording procedure, the block data yh,v of the time domain are transformed to the discrete cosine transform coefficients xk,l of the frequency domain by the DCT procedure.
The decompression and compression procedures of digital data of digital image codec of the prior art are opposite to each other. The digital image codec performs the 8-8 inverse discrete cosine transform (IDCT) procedure on the data flow to proceed the inverse transform procedure. The equation of the 8-8 IDCT procedure is:
      y          h      ,      y        =            ∑              k        =        0            7        ⁢                  ⁢                  ∑                  l          =          0                7            ⁢                          ⁢                        c          ⁡                      (            k            )                          ⁢                  c          ⁡                      (            l            )                          *                  x                      k            ,            l                          *                  COS          ⁡                      (                                                                                2                    ⁢                    h                                    +                  1                                16                            ⁢              k              ⁢                                                          ⁢              π                        )                          *                  COS          ⁡                      (                                                            (                                                            2                      ⁢                      v                                        +                    1                                    )                                16                            ⁢              l              ⁢                                                          ⁢              π                        )                              
wherein
            c      ⁡              (        0        )              =          1              2        ⁢                  2                      ,                    c        ⁡                  (          i          )                    =              1        /        2              ;  i is an integer, and i=1˜7. Please refer to U.S. Pat. No. 5,565,921 for the detail process of the digital image coder/decoder utilizing DCT procedure and IDCT procedure to compress and decompress digital images.
The main drawback of the digital image codec of the prior art is that the prior art uses the conventional row column decomposition method to divide 2-D IDCT operation into two 1-D IDCT operations. Therefore, the digital image codec of the prior art must wait for all 64 outcomes of the first 1-D IDCT operation to be obtained before performing a second 1-D IDCT operation. This waiting period prolongs the time to decompress digital images in the prior art. Moreover, the prior art further needs a buffer memory to buffer the 64 intermediate values, so the cost of the digital image codec is increased.
As mentioned in “Case study on discrete cosine transformation, 2D-DCT with linear processor arrays” reported by Ullrich Totzek, Fred Matthiesen, and Michael Boehner, etc. on EEC SPRITE research report A.2.c/Siemens/Y2m6/4, Jun. 1, 1990, this prior art enables the digital image codec to perform the second 1-D DCT operation on the partial outcomes of the first 1-D DCT operation while the first 1-D DCT operation is still processing other outcomes. Since the second 1-D DCT operation can be performed without waiting to obtain all the 64 outcomes of the first 1-D DCT operation, the time of calculation needed by the prior art can be substantially reduced.
However, the prior art illustrates a hardware architecture of a DCT processor and it is not a scalable architecture. Since the demand on the throughput of IDCT operation may vary with different systems. In the case that if the throughput of IDCT operation needs to be further speed up, the hardware of the prior art usually has to be redesigned. It will waste the hardware design resources, extend the design cycle, and fail to meet the time-to-market requirement.
Therefore, the major objective of the present invention is to provide a scalable system for IDCT and method thereof to solve the problems of the prior art.